The present invention relates generally to integrated circuits, and more particularly, to a multiplexer circuit.
Integrated circuits (ICs) such as microprocessors, microcontroller units (MCUs), systems-on-chips (SoCs), and application specific integrated circuits (ASICs) include various circuits, such as hard and soft intellectual property (IP) cores, latches, registers, and combinational logic circuits. ICs often include self-test mechanisms such as logic built-in-self-test (LBIST) to enable self-checking of logic implemented on the IC. For example, LBIST procedures are often integrated in ISO 26262 standard compliant automotive electric and electronic devices where testing of safety features is crucial.
For an IC that includes LBIST, to enable testing of the circuits of the IC, the IC is configured to operate in functional and LBIST modes. When the IC is in functional mode, the circuits operate normally and enable the operation of the IC as per the desired application. When the IC is in LBIST mode, the circuits operate in a test mode to check for logic errors. For LBIST, typically the IC is divided into several LBIST partitions. Each LBIST partition includes a test controller that generates an enable signal to activate LBIST in that partition, a pseudo random pattern generator (PRPG), a flip-flop, a two-input multiplexer circuit, a circuit-under-test (CUT), and a multi-input shift register (MISR). The CUT includes one or more scan chains for shifting patterns of data through the CUT. During LBIST, the flip-flop loads the test patterns into the scan chains based on a clock signal. The responses to the test patterns are received from the scan chains and stored in the MISR in a compressed form (also referred to as a resultant signature). Subsequently, the resultant signature is compared with a stored golden signature that is indicative of correct responses to the test patterns. When the resultant and golden signatures match, the test controller determines that the CUT is functioning correctly.
Generally, the LBIST partitions exchange functional signals with each other when the IC is in functional mode. However, during selective LBIST of one or more selected LBIST partitions, the remaining LBIST partitions may not be tested and hence, may be set or operating in functional mode. Thus, when a set of LBIST partitions must be tested and another set of LBIST partitions are in functional mode, an LBIST partition belonging to the first set that is being tested may exchange functional signals with circuits of one of more of the LBIST partitions of the second set. For instance, if a functional signal (hereinafter referred to as “random signal”) enters a LBIST partition while that partition is in LBIST mode, the random signal may lead to generation and storage of a false resultant signature in the MISR, thereby corrupting the LBIST execution. Such random signals are generally designated as x-signals and circuits such as flip-flops, latches, and memories propagate such x-signals to the LBIST partitions under test.
To ensure that x-signals do no enter an LBIST partition under test, x-signals are blocked or neutralized at the input of the LBIST partitions using x-bounding circuits. An x-bounding circuit includes a multiplexer circuit that is referred to as an x-bound multiplexer circuit. Each x-bound multiplexer circuit has first and second input terminals, a select terminal, and an output terminal. The first and second input terminals receive an x-signal and the test patterns, respectively. The select terminal receives the LBIST enable signal and the output terminal provides the x-signal or the test patterns based on the enable signal. When the LBIST partition is not being tested, the x-bound multiplexer circuit outputs the x-signal (the functional signal). When the LBIST partition is under test, the x-bound multiplexer circuit outputs the test patterns. Hence, the x-signal is blocked when the LBIST partition is under test, and is passed when the LBIST partition is not under test.
FIG. 1 is a schematic circuit diagram of a conventional two-input x-bound multiplexer circuit 100. The multiplexer circuit 100 includes first, second, and third CMOS inverters 102, 104, and 106, first and second transmission gates 108 and 110, and a fourth CMOS inverter 112 that are implemented using first through twelfth transistors 114-136.
The first CMOS inverter 102 is implemented using the first and second transistors 114 and 116. The first transistor 114 has a source terminal connected to a supply voltage Vdd and a gate terminal connected to a select input (SL) pin for receiving a select signal (SL). The second transistor 116 has a source terminal connected to ground, a gate terminal connected to the select input (SL) pin for receiving the select signal (SL), and a drain terminal connected to a drain terminal of the first transistor 114 for generating an inverted select signal (/SL). For example, the gate terminals of the first and second transistors 114 and 116 may be connected to an LBIST controller (not shown) for receiving the select signal (SL).
The second CMOS inverter 104 is implemented using the third and fourth transistors 118 and 120. The third transistor 118 has a source terminal connected to the supply voltage Vdd and a gate terminal connected to a first input (I1) pin for receiving a first input signal (I1). The fourth transistor 120 has a source terminal connected to ground, a gate terminal connected to the first input (I1) pin for receiving the first input signal (I1), and a drain terminal connected to a drain terminal of the third transistor 118 for generating an inverted first input signal. In an example, the gate terminals of the third and fourth transistors 118 and 120 are connected to a functional circuit (not shown) that includes the two-input multiplexer circuit 100 for receiving the x-signal as the first input signal (I1).
The third CMOS inverter 106 is implemented using the fifth and sixth transistors 122 and 124. The fifth transistor 122 has a source terminal connected to the supply voltage Vdd and a gate terminal connected to a second input (I2) pin for receiving a second input signal (I2). The sixth transistor 124 has a source terminal connected to ground, a gate terminal connected to the second input (I2) pin for receiving the second input signal (I2), and a drain terminal connected to a drain terminal of the fifth transistor 122 for generating an inverted second input signal. In an example, the gate terminals of the fifth and sixth transistors 122 and 124 are connected to a flip-flop (not shown) for receiving the test patterns as the second input signal (I2).
The first transmission gate 108 is implemented using the seventh and eighth transistors 126 and 128. The seventh transistor 126 has a source terminal connected to the drain terminal of the third transistor 118 for receiving the inverted first input signal and a gate terminal connected to the select input (SL) pin for receiving the select signal (SL). The eighth transistor 128 has a source terminal connected to the drain terminal of the third transistor 118 for receiving the inverted first input signal, a gate terminal connected to the drain terminal of the first transistor 114 for receiving the inverted select signal, and a drain terminal connected to a drain terminal of the seventh transistor 126 for outputting the inverted first input signal.
The second transmission gate 110 is implemented using the ninth and tenth transistors 130 and 132. The ninth transistor 130 has a source terminal connected to the drain terminal of the fifth transistor 122 for receiving the inverted second input signal and a gate terminal connected to the drain terminal of the first transistor 114 for receiving the inverted select signal. The tenth transistor 132 has a source terminal connected to the drain terminal of the fifth transistor 122 for receiving the inverted second input signal, a gate terminal connected to the select input (SL) pin for receiving the select signal (SL), and a drain terminal connected to a drain terminal of the ninth transistor 130 for outputting the inverted second input signal.
The fourth CMOS inverter 112 is implemented using the eleventh and twelfth transistors 134 and 136. The eleventh transistor 134 has a source terminal connected to the supply voltage Vdd and a gate terminal connected to the drain terminals of the seventh and ninth transistors 126 and 130 for receiving at least one of the inverted first and second input signals, respectively. The twelfth transistor 136 has a source terminal connected to ground, a gate terminal connected to the drain terminals of the seventh and ninth transistors 126 and 130 for receiving at least one of the inverted first and second input signals, respectively, and a drain terminal connected to a drain terminal of the eleventh transistor 134 for generating at least one of the first and second input signals (I1 and I2). The drain terminals of the eleventh and twelfth transistors 134 and 136 are connected to a circuit (not shown).
The first, third, fifth, seventh, ninth, and eleventh transistors 114, 118, 122, 126, 130, and 134 are p-channel metal-oxide semiconductor (PMOS) transistors, and the second, fourth, sixth, eighth, tenth, and twelfth transistors 116, 120, 124, 128, 132, and 136 are n-channel metal-oxide semiconductor (NMOS) transistors.
Based on a logic state of the select signal (SL), the multiplexer circuit 100 selects and outputs at least one of the first and second input signals (I1 and I2) at its output terminal. When the select signal (SL) is at a logic low state, the multiplexer circuit 100 selects and outputs the first input signal (I1) and when the select signal (SL) is high, the multiplexer circuit 100 selects and outputs the second input signal (I2).
However, with advancements in technology, the complexity of circuit designs of ICs has increased. To ensure correct evaluation of on-chip modules having such complex circuit designs, the SoC is divided into several LBIST partitions that include at least one x-bound multiplexer circuit. However, the addition of multiple x-bound multiplexer circuits leads to criticality in timing and power constraints. For instance, a complex SoC having 0.3 million flip-flops can have around 11 k x-bound multiplexer circuits. Thus, the overhead in terms of timing and power are high in such designs, thereby rendering the conventional x-bound multiplexer circuit inefficient for timing and power critical designs. For instance, the conventional x-bound multiplexer circuit cannot be used in SoCs that perform safety critical operations, such as opening of airbags in an automobile.
One known technique to overcome the aforementioned problem uses a high speed multiplexer circuit having high drive strength. The high speed multiplexer circuit is inserted at the input of the LBIST partition. The timing and power characteristics of the functional and test data-paths of the high speed multiplexer circuit that propagate the x-signals and the test patterns, respectively, are similar. However, the similarity of the two data-paths does not yield any benefit as the test data-path is generally static and does not have any timing requirement, whereas the functional data path is timing critical.
Therefore, it would be advantageous to have a two-input multiplexer circuit for blocking or neutralizing x-signals at the input of LBIST partitions of an SoC, reduces power consumption, and meets data path timing requirements.